Field of the Invention
The present invention relates to an insulated gate bipolar transistor (referred to as IGBT below) and, more particularly, to an IGBT having an increased latch-up breakdown voltage and short-circuit breakdown voltage.
Description of the Background Art
FIG. 1A is a plan view showing a structure of a conventional IGBT, and FIG. 1B is a sectional view taken along the line A-A' of FIG. 1A. As shown in FIGS. 1A and 1B, an N.sup.+ type buffer layer 2 is formed on a P type semiconductor substrate 1, and an N.sup.- type semiconductor layer 3 is formed on the N.sup.+ type buffer layer 2. A plurality of striped P type well regions 4 are selectively formed on the N.sup.- type semiconductor layer 3 by double diffusion. On each P type well region 4, two striped N.sup.+ type emitter regions 5 are selectively formed. Regions 6, which are located in the vicinity of portions of the surface of each P type well region 4 between the surfaces of the N.sup.- type semiconductor region 3, and each N.sup.+ type emitter region 5 are defined as channel regions. Gate insulation films 7, are provided on the channel regions 6, and gate electrodes 8 are formed thereon. Insulation films 9 are provided to cover the gate electrodes 8, and an emitter electrode 10 is formed thereon to electrically connect both with the P type well regions 4 and N.sup.+ type emitter regions 5. A collector electrode 11 is formed on the back surface of the P type semiconductor substrate 1. The plan view in FIG. 1A exhibits a state before the formation of the insulation films 9 and emitter electrode 10.
FIG. 2 is a circuit diagram showing an equivalent circuit of a cell of the IGBT. An N channel MOSFET 12 is formed in the vicinity of the channel regions 6. An PNP transistor 13 is formed of the P type semiconductor substrate 1, N.sup.- type semiconductor layer 3 and P type well region 4, and an NPN transistor 14 is formed of the N.sup.- type semiconductor layer 3, P type well region 4 and N.sup.+ type emitter region 5.
Electrons flow from the N.sup.+ type emitter regions 5 to the N.sup.- type semiconductor layer 3 through inversion layers formed in the channel regions 6 by applying a plus potential to the gate electrodes 8 while applying a plus potential to the collector electrode 11 and a minus potential to the emitter electrode 10. An electron current flowing in such a manner is represented by I.sub.e in FIG. 2. Holes of minority carriers are injected into the N.sup.- type semiconductor layer 3 from the P type semiconductor substrate 1. Some of the holes disappear by recombining with the aforementioned electrons and the remainder flow in the P type well regions 4 as a hole current I.sub.h. In this way, the IGBT functions basically as a bipolar transistor and, therefore, has an advantage that, as compared with a conventional power MOSFET, a lower ON state voltage and a larger current capacity can be implemented because the conductivity of the N.sup.- type semiconductor layer 3 is increased by virtue of a conductivity modulation.
On the other hand, as will be apparent from the equivalent circuit in FIG. 2, the IGBT cell has a parasitic PNPN thyristor structure formed of the PNP transistor 13 and NPN transistor 14. When both the transistors 13 and 14 are activated and the sum of current amplification factors .alpha..sub.1 and .alpha..sub.2 of the transistors 13 and 14 become equal to 1, the parasitic thyristor is conductive and latch-up occurs. With regard to its structure, the thickness of the N.sup.- type semiconductor layer 3 serving as a base of the PNP transistor 13 is very large as compared with a carrier diffusion length, and hence .alpha..sub.1 has a relatively small value. Additionally, the NPN transistor 14 can not be easily turned on because its base and emitter are short-circuited. Hence, the latch-up does not occur in the normal operation, and the IGBT cell functions as a composite device of the n channel MOSFET 12 and the PNP transistor 13. In such a case, since the base current of the PNP transistor 13 is controlled by the n channel MOSFET 12, it becomes possible that the main current I.sub.C flowing from the collector electrode 11 is controlled by a control signal applied to the gate electrodes 8. The following relation holds EQU I.sub.C =I.sub.E =I.sub.e +I.sub.h ( 1)
where I.sub.E is a current flowing in the emitter electrode 10.
However, when the main current I.sub.C is increased due to any external cause such as load short-circuiting, the electron current I.sub.e and hole current I.sub.h are increased. Then, when the hole current I.sub.h exceeds a certain value, the NPN transistor 14 becomes conductive because of the voltage drop in resistance R.sub.B in the P type well regions 4, and its current amplification factor .alpha..sub.2 is increased. This causes .alpha..sub.1 +.alpha..sub.2 =1 to be satisfied, so that the parasitic thyristor becomes conductive. Thus, the IGBT is latched up. In such a state, the main current I.sub.C in the IGBT can hardly be controlled by the control signal applied to the gate electrodes 8, and therefore an excessive main current I.sub.C flows without limitation. Even if the IGBT is not latched up, the IGBT may be destroyed by a thermal breakdown since a large main current I.sub.C continues to flow. Accordingly, with regard to the conventional IGBT, it is desired to increase its latch-up breakdown voltage and short-circuit breakdown voltage.